Digital Signal Transceiver Generation (DSTG) State Model

The Digital Signal Transceiver Generation (DSTG) programming model for vector signal generators and the generation functionality of vector signal transceivers has three main states. The state of the instrument at a given time affects the actions you can take during that time.

The following diagram depicts the state model for the DST instrument when programmed with DSTG software.

Figure 1. DSTG State Model


The states are as follows:

  • Configuration—(Idle) You can program all session properties in the Configuration state; however, properties are not yet applied to the instrument in this state. Therefore, the actual instrument configuration may not match the values of the properties in the session. The DSTG instrument does not generate a signal in the Configuration state.
    Note When you read a property, DSTG may analyze many properties in the current configuration in order to return the coerced value for that property or attribute. In general, avoid reading any properties until you have finished changing all the properties you want to change. Otherwise, you may encounter errors if a property is read while the configuration is in an inconsistent state.
  • Committed—Call DSTG Commit from the Configuration state to perform the following actions:
    • Verifies the settings of all properties.
    • Validates the specified configuration.
    • Writes all settings to the hardware modules.
    • Transitions to the Committed state.

    If any properties are changed while in the Committed state, the session implicitly transitions back to the Configuration state and the hardware configuration reflects the previously committed properties or attributes.

  • Generation—(Running) The instrument is either waiting for a trigger or is generating a signal. Session properties reflect the current state of the instrument.
  • Note You can call the DSTG Close VI from any state. Calling this VI stops signal generation and exits the state machine.