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This document contains the LabVIEW 2019 FPGA Module known issues that were discovered before and since the release of LabVIEW 2019 FPGA Module. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.
The LabVIEW 2019 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.
The following items are known issues in LabVIEW 2018 FPGA Module sorted by Date.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| 404665 Return | The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO. Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.
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| 660205 Return | When using the C API, some debugging tools may report a dynamic memory leak When using the FPGA Interface C API, a memory leak may be reported by third-party debugging tools. This memory leak will only cause memory growth if the NiFpga_Initialize() and NiFpga_Finalize() functions are called continually or in a loop, and should not impact normal usage. Workaround: Call NiFpga_Initialize() and NiFpga_Finalize() only once in the application, during the program initialization and exit procedures respectively.
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| 733478 Return | Opening more than 127 concurrent FPGA Interface sessions causes a crash Attempting to open more than 127 concurrent FPGA sessions using the LabVIEW FPGA Interface API, the FPGA Interface C API or the FPGA Interface Python API causes a crash. Workaround: Modify the value of the TableSegmentSize token in the nirio.ini file to be a power of two greater than or equal to the number of sessions required.
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| 713545 Return | Changing the bitfile contents on disk while a VI with a reference to that bitfile is open does not force the new bitfile to be loaded Running a VI containing an Open FPGA VI Reference node pointed to a bitfile on disk and then changing the contents of that bitfile (i.e. deleting an old bitfile and renaming another bitfile to use the original bitfile's name) does not load and run the new bitfile contents on subsequent runs. Workaround: Browse to the bitfile through the Configure Open FPGA VI Reference dialog and select the bitfile again. The node creates a memory copy of the bitfile contents which introduces the possibility of an inconsistency between the bitfile contents on disk and the in memory copy. The workaround forces an update an update to the in memory copy.
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| 708799 Return | Moving a VI from the Host to FPGA that contains a variable sized array connected to a channel wire causes a Code Generation error Moving and then attempting to compile a VI created on the Host to an FPGA target when that VI contains a variable sized array connected to a channel writer endpoint causes a Code Generation error stating "LabVIEW cannot determine the size of the array on the control or indicator because arrays of different sizes are wired to separate calls to the non-reentrant VI. Ensure that all calls to the VI use array inputs of the same size." In addition, creating a variable sized array in an FPGA VI and then using that with a Channel Wire also causes the same Code Generation error to be thrown. Workaround: Remove and then recreate the channel writer endpoint, channel reader endpoint and array constants when the VI is under an FPGA target.
|
The following items are known issues in LabVIEW 2018 FPGA Module sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| FPGA Interface C API | ||||||
| 660205 Return | When using the C API, some debugging tools may report a dynamic memory leak When using the FPGA Interface C API, a memory leak may be reported by third-party debugging tools. This memory leak will only cause memory growth if the NiFpga_Initialize() and NiFpga_Finalize() functions are called continually or in a loop, and should not impact normal usage. Workaround: Call NiFpga_Initialize() and NiFpga_Finalize() only once in the application, during the program initialization and exit procedures respectively.
| |||||
| Functions, VIs, and Express VIs | ||||||
| 404665 Return | The FIFO.configure method only clears the FIFO contents if a new Actual Depth is set According to the LabVIEW FPGA help documentation, the FIFO.configure method will clear the contents of the host-side FIFO buffer. This is not true if the FIFO.configure method does not change the "Actual Depth" of the host-side FIFO. Workaround: Use FIFO.Stop and FIFO.Start to clear the host-side FIFO buffer.
| |||||
| 713545 Return | Changing the bitfile contents on disk while a VI with a reference to that bitfile is open does not force the new bitfile to be loaded Running a VI containing an Open FPGA VI Reference node pointed to a bitfile on disk and then changing the contents of that bitfile (i.e. deleting an old bitfile and renaming another bitfile to use the original bitfile's name) does not load and run the new bitfile contents on subsequent runs. Workaround: Browse to the bitfile through the Configure Open FPGA VI Reference dialog and select the bitfile again. The node creates a memory copy of the bitfile contents which introduces the possibility of an inconsistency between the bitfile contents on disk and the in memory copy. The workaround forces an update an update to the in memory copy.
| |||||
| 733478 Return | Opening more than 127 concurrent FPGA Interface sessions causes a crash Attempting to open more than 127 concurrent FPGA sessions using the LabVIEW FPGA Interface API, the FPGA Interface C API or the FPGA Interface Python API causes a crash. Workaround: Modify the value of the TableSegmentSize token in the nirio.ini file to be a power of two greater than or equal to the number of sessions required.
| |||||
| 708799 Return | Moving a VI from the Host to FPGA that contains a variable sized array connected to a channel wire causes a Code Generation error Moving and then attempting to compile a VI created on the Host to an FPGA target when that VI contains a variable sized array connected to a channel writer endpoint causes a Code Generation error stating "LabVIEW cannot determine the size of the array on the control or indicator because arrays of different sizes are wired to separate calls to the non-reentrant VI. Ensure that all calls to the VI use array inputs of the same size." In addition, creating a variable sized array in an FPGA VI and then using that with a Channel Wire also causes the same Code Generation error to be thrown. Workaround: Remove and then recreate the channel writer endpoint, channel reader endpoint and array constants when the VI is under an FPGA target.
| |||||
Document last updated on 5/17/2019