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Each issue appears as a row in the table and includes the following fields:
| ID | Known Issue | |||||||||||||||||
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| 467086 | The niRFRIO DSP 1.0.0 FPGA.lvlib:Fractional Decimator VI does not meet the 85 dBc of SFDR specification at certain output sample rates The fractional decimator SFDR specification is 85 dBc, but at certain output sample rates the SFDR can be as bad as 50 dBc. This can only happen in certain output sample rate regions. To determine a problem output sample rate region, complete the following steps:
(9.78 / (Integer Decimation Factor * output sample rate)) - RoundDown( 9.78 / Integer Decimation Factor * output sample rate) < (2-8) If the previous equation equals true, then the selected output sample rate region is problematic. Workaround: Select a different output sample rate outside the problem regions.
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| 461909 | The niRFRIO DSP 1.0.0 FPGA.lvlib:Fractional Decimator VI causes trigger jitter for low output sample rate configurations There is inconsistent timing between assertions of the boolean output valid and output calculated indicators in the niRFRIO DSP 1.0.0 FPGA.lvlib:Fractional Decimator VI. Applications that rely on those signals to align triggers with post-processed data will experience trigger jitter. The faulty behavior happens when the output sample rate is set to less than 0.0625 samples per cycle. Applications suffering from this source of trigger jitter include NI-RFSA and instrument driver FPGA extensions. Workaround: N/A
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| 364860 | A deadlock can occur when creating two peer-to-peer streams between two devices in opposite directions concurrently Workaround: To avoid the deadlock, serialize the calls to the niP2P Create Peer to Peer Stream VIs.
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| 365340 | Running a VST sample project FPGA VI on a development computer with simulated I/O context causes LabVIEW to hang Running a VST Sample Project FPGA VI on the development computer with simulated I/O context causes LabVIEW to hang because of the way LabVIEW FPGA allocates and uses the DRAM memory primitive when executing in the development computer context. Workaround: There is no workaround to achieve full functionality, that is, to achieve the same waveform and record memory size available when running on hardware. However, you can use the following instructions to work around the LabVIEW memory issue:
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| 363009 | The NI PXIe-5644R, NI PXIe-5645R, NI PXIe-5646R device may occasionally appear outside the chassis in MAX when the device is installed for the first time The NI PXIe-5644R, NI PXIe-5645R, or NI PXIe-5646R device may occasionally appear outside the chassis in Measurement & Automation Explorer (MAX) when the hardware/software is installed for the first time. The device should still function properly. Workaround: Restart the machine to get the device to appear in MAX properly.
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| 364518 | Error –52018. A hardware failure has occurred. The operation could not be completed as specified This error may occur when an instrument design VI accesses elements of an FPGA VI that are inside a Single Cycle Timed Loop (SCTL) that does not have a running clock. In this case, the problem is not a hardware failure and can be fixed by enabling the clock of the SCTL. Workaround: Ensure that the SCTL clocks are running before calling the VI that returns the error.
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| 453026 | When closing a newly created Simple VSA/VSG sample project, selecting Save in the Save Changes (Close Project) dialog box does not work When closing a newly created Simple VSA/VSG sample project, selecting Save in the Save Changes (Close Project) dialog box does not work and the Save Changes (Close Project) dialog box does not close. Workaround: There are two possible workarounds for this issue:
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| 369338 | A dialog box prompts you to save a file when you create a VST sample project in localized LabVIEW The first time you create a VST sample project (Simple VSA/VSG or Simple VST Streaming) in localized LabVIEW after installing instrument design libraries 2012.1, a dialog box prompts you to save niLvFpga_Open_PXIe-5644R.vi or similar. Workaround: Click Save in the dialog box to continue creating the sample project.
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| 392126 | The niVST Calibration.lvlib:Self-Calibrate.vi leaks memory when loading and unloading When using Self-Calibrate VI from the NI VST Calibration palette to self-calibrate the NI PXIe-5644R or NI PXIe-5645R, a memory leak may occur when loading and unloading the VI repeatedly. Workaround: Keep the Self-Calibrate VI in memory. For example, in your top-level VI, create a "dummy" subVI that includes one instance of the Self-Calibrate VI to keep the Self-Calibrate VI loaded in memory. For applications that optimize memory usage where it is not acceptable to keep the Self-Calibrate VI in memory, you can minimize the memory leak by keeping a Timed Loop in memory. A memory leak will still exist, but it will be considerably smaller.
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| 414557 | Error –2147220623 occurs when a Simple VSA/VSG sample project created in design library 1.0 is run in design library 13.5 Running a Simple VSA/VSG sample project created with NI LabVIEW 2012 Support for NI PXIe-5644R 1.0.0 with current VST support returns error -2147220623. Workaround: Complete the following steps to workaround this issue:
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| 364736 | Waveform Sequencer does not generate any samples if the Set Priming Depth VI is set to a value of 4 samples or less The Retrieve Waveform Sample FPGA VI of the Waveform Sequencer library does not generate any samples if you set the generation priming depth to a value less than or equal to 4 in the Set Priming Depth VI of the Waveform Sequencer host library. Workaround: Configure the Set Priming Depth VI to a value of at least 5 samples; otherwise do not call the Set Priming Depth VI. If you do not call the Set Priming Depth VI, the application uses the default priming depth.
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| 452057 | The default value for Maximum outstanding requests for data on VST DRAM memory items is insufficient for maximum DRAM throughput When creating a new DRAM memory item, the default value for Maximum outstanding requests for data is 32. This value must be changed to 64 to achieve maximum DRAM throughput on VST devices. Workaround: Right-click a DRAM memory item under an FPGA Target in your LabVIEW project, and select Properties. In the General category, change the value for Maximum outstanding requests for data to 64.
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| 425439 | When NI-RFSA and NI-RFSG both export a signal to the same external trigger line on a VST, LabVIEW does not return an error It is possible to export two different signals to the same external trigger line on a VST, for example, NI-RFSG exports a Marker Event to PFI0, and NI-RFSA exports a Start Trigger to PFI0. However, LabVIEW does not return an error when this occurs, which causes only the last item that is configured within either driver to export its signal. Workaround: Avoid exporting signals from both drivers to the same external trigger line.
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| 411948 | Error –373104 occurs when a hyphen character is used in a configuration list name When creating a configuration list in NI-RFSA or NI-RFSG on a VST target, the use of hyphens in the configuration list name results in error -373104, the specified configuration list name is invalid. Workaround: Avoid using hyphen characters in configuration list names.
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| 464021 | The 802.11ac 80 MHz bandwidth and 160 MHz bandwidth with channel tracking enabled specifications are marked as warranted in the NI PXIe-5646R Specifications The 802.11ac 80 MHz bandwidth and 160 MHz bandwidth with channel tracking enabled specifications are typical specifications. These specifications should be marked as typical specifications instead of warranted in the NI PXIe-5646R Specifications. Workaround: N/A
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Related Topics:
Contact NI regarding this document or issues in the document. If you contact NI in regards to a specific issue, reference the ID number given in the document. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting NI). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also contact us if you find a workaround for an issue that is not listed in the document.