New NI LabVIEW FPGA Features
New LabVIEW 8.6 Features
New LabVIEW 8.5 Features
New LabVIEW 8.2 Features
LabVIEW 8.0 Features
LabVIEW 7.1 Features
New LabVIEW 8.6 FeaturesView the Webcast "What's New in LabVIEW FPGA 8.6" Enhanced Behavioral SimulationFor more efficient development, you can use enhanced behavioral simulation to run the code on the development computer and verify functionality before compilation. Additionally, in LabVIEW 8.6, you can use LabVIEW programs that assert test vectors or interactive values to the input I/O nodes in the field-programmable gate array (FPGA). Capture the outputs for verification and visualization of FPGA behavior, run the host at the same time as the FPGA on the development computer, and get simulated register and DMA transfers between the simulated FPGA and host code. With these new features, you can create a test bench for the FPGA code and simulate the entire system without always compiling to check logic. FFT and Other New IPIn LabVIEW 8.6, you can now implement FFT with windowing on the FPGA. This is one of the most requested features, and NI has delivered a customizable IP core that can execute FFT, inverse FFT, multiple bin sizes, and multiple throughput settings. NI also is releasing rational resampling, divide, square root, adaptive filters, and fixed-point overflow handling functions. Fixed-Point SupportThe fixed-point data type is now supported on nearly every FPGA function input. This includes support for DMA, memory, filters, PID, FFT, and all arithmetic. Additionally, the fixed-point data type offers an option to add an overflow bit carried on the wire. NI will continue to enhance fixed-point support in the future to unlock this unique engineering challenge needed to work with resource-constrained targets. Component-Level IP (CLIP)Component-level IP is a new way to import and use external IP written in a hardware description language (HDL). Implementations instantiated with CLIP run in parallel with the LabVIEW diagram, and you communicate to them through user-created I/O nodes. With some hardware targets, you can use CLIP to talk directly to I/O pins. CLIP functions open the FPGA platform further to include all types of IP, which may be better suited to run in parallel rather than in data flow like the current HDL Node runs. LabVIEW 8.5 FeaturesFPGA Project WizardThe new FPGA Project Wizard helps you create a complete LabVIEW Project with the FPGA target and I/O configured and ready to program. Because it can directly link to the existing FPGA Wizard, you can quickly generate functional code for analog and digital I/O, counter, and quadrature encoder measurements. The FPGA Project Wizard is enhanced with new DMA options for FPGA and host code generation.
Control, Filtering, and Signal Generation IPThe LabVIEW FPGA Module 8.5 includes new IP in the FPGA palette as well as enhanced existing IP for improved resource use on the FPGA.
Modularity and Code Reuse FeaturesI/O name controls - Put I/O nodes, methods, and properties inside subVIs specifying the I/O item through a wire. Clock controls - Use a wire to specify which clock, such as an onboard or derived clock, to use in a particular single-cycle timed loop.
Enhanced feedback node - Place a feedback node anywhere in a block diagram to escape the context of a loop. Feedback nodes can be very useful for state storage or pipelining and now work anywhere, including subVIs. LabVIEW Statechart ModuleNI now offers additional ways to program FPGAs graphically. Many designers prefer using statecharts to represent the system they want to build. With this new module supporting LabVIEW FPGA, designers can not only represent FPGA-based systems with statecharts but also program them with the same visual paradigm. Pioneer-Level Support for Fixed-Point Data TypeThere is a new fixed-point data type in LabVIEW that is especially useful for FPGA programming. Previously, LabVIEW FPGA only supported integers. However, with support for new fixed-point data types, engineers can bring fractional numbers and arbitrary bit-width data types to FPGA programming. LabVIEW 8.5 features fixed-point support for a small number of primitive math and comparison functions. Future releases may expand support for this important data type. New LabVIEW 8.2 FeaturesFPGA Math and Analysis IPThe LabVIEW FPGA Module 8.2 provides new native analysis functions so you can reuse code for basic signal processing and control functionalities common to FPGAs. This new IP includes:
FPGA WizardYou can design FPGA I/O and timing for your intelligent DAQ applications with the FPGA Wizard. Using this configuration-based wizard, you can select the timing and synchronization between your FPGA device and host VI. After selecting your timing, you can configure your analog, digital, counter, or quadrature encoder I/O. Once configured, you can save your configuration and generate basic FPGA code and host code. You can then incorporate additional code to complete your application functions such as control algorithms, data logging, or networking of your data.
New Memory VIsWith the new memory read and write interface, you can now access all 80 KB of memory on 1M gate devices and all 190 KB of memory on 3M gate devices. You can use memory to store data for waveform generation or data logging without using arrays that inefficiently use FPGA gates. LabVIEW 8.0 FeaturesLabVIEW ProjectWith the LabVIEW Project, you not only can target and open VIs in LabVIEW for Windows, the LabVIEW FPGA Module, the LabVIEW Real-Time Module, and other LabVIEW modules simultaneously but also develop LabVIEW FPGA applications. As seen below, you can use the LabVIEW Project to create and manage all FPGA resources including:
DMA Data TransfersThe LabVIEW FPGA Module 8.0 DMA capabilities eliminate throughput limitations between the FPGA device and host. While FPGAs on reconfigurable I/O (RIO) devices can run at rates up to 20 MHz, the fastest data-streaming rate without DMA is approximately 1 MB/s. The LabVIEW FPGA Module 8.0 implements DMA on all National Instruments R Series and CompactRIO devices for at least a 20 times increase in data-streaming rates between the FPGA and a host application compared to other implementations such as using interrupt requests. DMA provides a direct data-to-RAM link on the host machine. Relying on the host processor to stream data from the device to the host often leads to latencies and causes a data transfer bottleneck. Using interrupt requests also consumes processor clock cycles and increases the overall load on a host CPU. With LabVIEW 8, you gain more efficient device-to-host and host-to-device data transfers that bypass the CPU, creating a higher-performance data acquisition system for all applications. To use DMA, simply create two memory buffers - one in memory on the FPGA device and one in memory on the host processor - and LabVIEW efficiently and transparently transfers data over the PCI bus. The LabVIEW FPGA Module 8.0 uses FPGA FIFOs configured for DMA to write and read to DMA memory and uses FPGA invoke methods on the host side to create, write, and read from host memory. DMA significantly enhances RIO hardware for applications such as buffered intelligent data acquisition, streaming digital communication devices, in-vehicle data acquisition, and online machine condition monitoring.
Drag-and-Drop FPGA I/OWith LabVIEW FPGA, you quickly can access RIO device I/O through specific device I/O functions. (However, the LabVIEW FPGA function palettes mentioned in this document are specific to FPGA execution targets and contain functions only available when targeted to an FPGA device or FPGA device emulator.) The LabVIEW FPGA Module gives you direct single-point access to analog and digital I/O on National Instruments RIO hardware. With the LabVIEW 8.0 FPGA Module, you can directly drag and drop I/O from the LabVIEW Project window onto the block diagram of your FPGA VI. The LabVIEW FPGA Module offers many device I/O functions, including:
LabVIEW 7.1 FeaturesSingle-Cycle Timed LoopThe LabVIEW timed-loop structure executes a loop at the period you specify. Use the timed loop to develop VIs with multirate timing capabilities, precise timing, and feedback generation on loop execution or to dynamically change timing characteristics or several execution priority levels. Read a tutorial for more information on the timed loop. The LabVIEW FPGA single-cycle timed loop is a specialized timed loop with which you can develop LabVIEW FPGA applications as efficiently (in terms of speed and space) as hand-coded HDL programming. The single-cycle timed loop is similar to a clocked process in VHDL. All of the LabVIEW code in the loop is combinatorial logic on the FPGA, where inputs are from components such as digital input functions, controls, or left-shift registers and outputs are digital output functions, indicators, and right-shift registers. It is easy to take advantage of a single-cycle timed loop - use it as you do a standard while loop. The single-cycle timed loop ensures that all code within the loop executes in a single clock cycle (25 ns). While there are some limitations to the single-cycle timed loop, such as ensuring that all the code inside it can execute within a clock cycle, using it can result in extremely efficient code for executing digital I/O and simple logic and signal processing. Learn about the single-cycle timed loop functions and I/O nodes in LabVIEW FPGA. HDL Interface NodeYou can integrate existing HDL IP directly into a LabVIEW FPGA VI using the HDL interface node and represent this code as a single function block within LabVIEW. You then can reuse this code within the same application or in other applications using the same function block. If you have a block of HDL code to use in an FPGA VI, you can either enter your VHDL code directly into the HDL interface node or refer to external .vhd files rather than rewriting the code in LabVIEW.
LabVIEW Block Diagram Integrating Custom VHDL |
Each release of the NI LabVIEW FPGA Module includes new usability features, FPGA intellectual property (IP) or functions, performance enhancements, scheduled bug fixes, and more.
Control - Included in the PID Toolkit, the proportional integral derivative (PID) block in FPGA now works with multiple channels, so users can input an array of channels into the same PID logic on the FPGA. This enhancement is especially important for high-channel-count applications. The number of possible channels rose from 8 to 256 for a 1-million gate target. Additionally, the single-channel benchmark is three times faster and uses almost 20 percent fewer FPGA resources.
Filtering - All filters are also compatible with multiple channels. Additionally, LabVIEW FPGA includes a new notch filter, rounding out the existing Butterworth highpass and lowpass filters.
Signal Generation - In addition to the existing sine generator, LabVIEW FPGA now features a square wave generator and noise generators (Gaussian and white).
